RoHs

2-input AND gate; open drain 2-input AND gate; open drain; TTL input 2-input EXCLUSIVE-OR gate 2-input NAND gate; open drain 3-input EXCLUSIVE-OR gate 3-to-8 line decoder/demultiplexer; inverting 3-to-8 line decoder/demultiplexer; inverting; TTL input 8-bit addressable latch 8-bit addressable latch; TTL-enabled 8-bit dual supply translating transceiver; 3-state 8-bit parallel-in/serial out shift register 8-bit parallel-in/serial out shift register; TTL-enabled 8-bit serial-in, parallel-out shift register 8-bit serial-in, parallel-out shift register; TTL-enabled 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state; TTL-enabled 8-bit shift register with input flip-flops 8-bit shift register with input flip-flops; TTL-enabled 8-bit shift register with output register 8-bit shift register with output register; TTL-enabled 8-stage shift-and-store bus register 8-stage shift-and-store bus register; TTL-enabled Buffer with open-drain output Buffer with open-drain output; TTL input Buffers with open-drain outputs Dual 4-input AND gate Dual 4-input NAND gate Dual 4-input NAND gate; TTL input Dual 4-input NOR gate Dual 4-input NOR gate; TTL input Dual buffer gate dual buffer; Schmitt-trigger Dual D-type flip-flop with set and reset; positive-edge trigger Dual D-type flip-flop with set and reset; positive-edge trigger; TTL enabled Dual D-type flip-flop with set and reset; positive-edge trigger; TTL input dual inverter dual inverter; Schmitt-trigger Dual unbuffered inverters Hex buffer with open-drain outputs Hex buffer/line driver; 3-state Hex buffer/line driver; 3-state; TTL input Hex D-type flip-flop with reset; positive-edge trigger Hex D-type flip-flop with reset; positive-edge trigger; TTL input Hex inverter Hex inverter/line driver (3-state) Hex inverter/line driver (3-state); TTL input Hex inverter; open-drain Hex inverter; open-drain; TTL input Hex inverter; TTL input Hex inverting Schmitt trigger Hex inverting Schmitt trigger with 5 V tolerant input Hex inverting Schmitt trigger; TTL input Inverter with open-drain output Inverters with open-drain outputs Low Voltage and High Speed SPDT Analog Switch with True Isolation Low-power configurable multiple function gate Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state Octal buffer/line driver; 3-state Octal buffer/line driver; 3-state; bus-hold Octal buffer/line driver; 3-state; inverting Octal buffer/line driver; 3-state; inverting; TTL-enabled Octal buffer/line driver; 3-state; TTL-enabled Octal Buffers/Drivers with 3-State Outputs Octal bus transceiver; 3-state Octal bus transceiver; 3-state; bus-hold Octal bus transceiver; 3-state; TTL-enabled Octal D-type flip-flop with data enable; positive-edge trigger Octal D-type flip-flop with data enable; positive-edge trigger; TTL input Octal D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop with reset; positive-edge trigger; TTL input Octal D-type flip-flop; positive edge-trigger; 3-state Octal D-type flip-flop; positive edge-trigger; 3-state; TTL input Octal D-type transparent latch; 3-state Octal D-type transparent latch; 3-state; TTL input Octal dual supply translating transceiver; 3-state Quad 2-input AND gate Quad 2-input AND gate; TTL input Quad 2-input EXCLUSIVE-OR gate Quad 2-input EXCLUSIVE-OR gate; TTL enabled; TTL input Quad 2-input NAND gate Quad 2-input NAND gate; open-drain Quad 2-input NAND gate; open-drain; TTL input Quad 2-input NAND gate; TTL input Quad 2-input NAND Schmitt trigger Quad 2-input NAND Schmitt trigger; TTL input Quad 2-input NOR gate Quad 2-input NOR gate; TTL input Quad 2-input OR gate Quad 2-input OR gate; TTL input Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Quad buffer/line driver; 3-state Quad buffer/line driver; 3-state; TTL input Single 2-input AND gate Single 2-input AND gate; TTL input Single 2-input multiplexer Single 2-input NAND gate Single 2-input NAND gate; TTL input Single 2-input NOR gate Single 2-input NOR gate; TTL input Single 2-input OR gate Single 2-input OR gate; TTL input Single 3-input AND gate Single 3-input NAND gate Single 3-input NOR gate Single 3-input OR gate Single buffer single buffer/line driver single buffer/line driver; TTL input single inverter single inverter; Schmitt-trigger single inverter; Schmitt-trigger; TTL input single inverter; TTL input Single inverting buffer/line driver; 3-state Single Schmitt trigger buffer Single Schmitt trigger buffer; TTL input Triple 3-input AND gate Triple 3-input AND gate; TTL input Triple 3-input NAND gate Triple 3-input NAND gate; TTL input Triple 3-input NOR gate Triple 3-input NOR gate; TTL input Triple 3-input OR gate Triple 3-input OR gate; TTL input Unbuffered inverter

1 2 3 4 6 8

1.2~5.5 1.2-3.6 1.2-5.5 1.5-5.5 1.5V~5.5V 1.65~3.6 1.65~5.5 1.65-3.6 1.65-5.5 1.65V~5.5V 2.0-5.5 2.0-6.0 2.5-5.5 2.7~6 2.7V~5.5V 2~6 2-5.5 2V~5.5V 2V~6V 4.5-5.5 4.5V~5.5V

- 100nA 10nA 10uA 160uA 1uA 200uA 20uA 2uA 40uA 4mA 4uA 5.2mA 80uA 8uA

-40 to 125℃